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CMOS DIGITAL INTEGRATED CIRCUITS Analysis and Design pdf eBook/ Notes download
Pankaj Yadav

CMOS DIGITAL INTEGRATED CIRCUITS Analysis and Design pdf eBook/ Notes download

Pankaj Yadav | 22-Jun-2016 |
CMOS DIGITAL INTEGRATED CIRCUITS , Analysis and Design , Introduction , FABRICATION OF MOSFETs , MOS TRANSISTOR , MODELING OF MOS TRANSISTORS USING SPICE , MOS INVERTERS: STATIC CHARACTERISTICS , MOS INVERTERS: SWITCHING CHARACTERISTICS AND INTERCONNECT EFFECTS , COMBINATIONAL MOS LOGIC CIRCUITS , SEQUENTIAL MOS LOGIC CIRCUITS , DYNAMIC LOGIC CIRCUITS , SEMICONDUCTOR MEMORIES , LOW-POWER CMOS LOGIC CIRCUITS , BiCMOS LOGIC CIRCUITS , VLSI DESIGN METHODOLOGIES , CHIP INPUT AND OUTPUT (O) CIRCUITS , DESIGN FOR MANUFACTURABILITY , DESIGN FOR TESTABILITY ,

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INDEX

1 INTRODUCTION 1
1.1 Historical Perspective 1
1.2 Objective and Organization of the Book 5
1.3 A Circuit Design Example 8
2 FABRICATION OF MOSFETs 20
2.1 Introduction 20
2.2 Fabrication Process Flow: Basic Steps 21
2.3 The CMOS nWell Process 29
2.4 Layout Design Rules 37
2.5 Full-Custom Mask Layout Design 40
References 44
Exercise Problems 45
3 MOS TRANSISTOR 47
3.1 The Metal Oxide Semiconductor (MOS) Structure 48
3.2 The MOS System under External Bias 52
3.3 Structure and Operation of MOS
Transistor (MOSFET) 55
3.4 MOSFET Current-Voltage Characteristics 66
3.5 MOSFET Scaling and Small-Geometry Effects 81
3.6 MOSFET Capacitances 97
References 110
Exercise Problems 111
vi. 4 MODELING OF MOS TRANSISTORS
USING SPICE 117
Contents
4.1 Basic Concepts 118
4.2 The LEVEL 1 Model Equations 119
4.3 The LEVEL 2 Model Equations 123
4.4 The LEVEL 3 Model Equations 130
4.5 Capacitance Models 131
4.6 Comparison of the SPICE MOSFET Models 135
References 137
Appendix: Typical SPICE Model Parameters 138
Exercise Problems 139
5 MOS INVERTERS: STATIC CHARACTERISTICS 141
5.1 Introduction 141
5.2 Resistive-Load Inverter 149
5.3 Inverters with n-Type MOSFET Load 160
5.5 CMOS Inverter 172
References 190
Exercise Problems 191
6 MOS INVERTERS: SWITCHING CHARACTERISTICS
AND INTERCONNECT EFFECTS 196
6.1 Introduction 196
6.2 Delay-Time Definitions 198
6.3 Calculation of Delay Times 200
6.4 Inverter Design with Delay Constraints 210
6.5 Estimation of Interconnect Parasitics 222
6.6 Calculation of Interconnect Delay 234
6.7 Switching Power Dissipation of CMOS Inverters 242
References 250
Appendix: Super Buffer Design 251
Exercise Problems 254
7 COMBINATIONAL MOS LOGIC CIRCUITS 259
7.1 Introduction 259
7.2 MOS Logic Circuits with Depletion nMOS Loads 260
7.3 CMOS Logic Circuits 274
7.4 Complex Logic Circuits 281
7.5 CMOS Transmission Gates (Pass Gates) 295
References 305
Exercise Problems 306
8 SEQUENTIAL MOS LOGIC CIRCUITS 312 vii
8.1 Introduction 312 Contents
8.2 Behavior of Bistable Elements 314
8.3 The SR Latch Circuit 320
8.4 Clocked Latch and Flip-Flop Circuits 326
8.5 CMOS D-Latch and Edge-Triggered Flip-Flop 334
Appendix: Schmitt Trigger Circuit 341
Exercise Problems 345
9 DYNAMIC LOGIC CIRCUITS 350
9.1 Introduction 350
9.2 Basic Principles of Pass Transistor Circuits 352
9.3 Voltage Bootstrapping 365
9.4 Synchronous Dynamic Circuit Techniques 368
9.5 High-Performance Dynamic CMOS Circuits 378
References 395
Exercise Problems 396
10 SEMICONDUCTOR MEMORIES 402
10.1 Introduction 402
10.2 Read-Only Memory (ROM) Circuits 405
10.3 Static Read-Write Memory (SRAM) Circuits 417
10.4 Dynamic Read-Write Memory (DRAM) Circuits 435
References 447
Exercise Problems 447
11 LOW-POWER CMOS LOGIC CIRCUITS 451
11.1 Introduction 451
11.2 Overview of Power Consumption 452
11.3 Low-Power Design Through Voltage Scaling 463
11.4 Estimation and Optimization of Switching Activity 474
11.5 Reduction of Switched Capacitance 480
11.6 Adiabatic Logic Circuits 482
References 489
Exercise Problems 490
12 BiCMOS LOGIC CIRCUITS 491
12.1 Introduction 491
12.2 Bipolar Junction Transistor (BJT):
Structure and Operation 494
viii 12.3 Dynamic Behavior of BJTs 509
12.4 Basic BiCMOS Circuits: Static Behavior 516
Contents 12.5 Switching Delay in BiCMOS Logic Circuits 519
12.6 BiCMOS Applications 524
References 529
Exercise Problems 530
13 CHIP INPUT AND OUTPUT (O) CIRCUITS 534
13.1 Introduction 534
13.2 ESD Protection 535
13.3 Input Circuits 538
13.4 Output Circuits and L(di/dt) Noise 543
13.5 On-Chip Clock Generation and Distribution 549
13.6 Latch-Up and Its Prevention 555
References 562
Exercise Problems 563
14 VLSI DESIGN METHODOLOGIES 566
14.1 Introduction 566
14.2 VLSI Design Flow 569
14.3 Design Hierarchy 570
14.4 Concepts of Regularity, Modularity and Locality 573
14.5 VLSI Design Styles 576
14.6 Design Quality 586
14.7 Packaging Technology 589
14.8 Computer-Aided Design Technology 592
References 593
Exercise Problems 594
15 DESIGN FOR MANUFACTURABILITY 598
15.1 Introduction 598
15.2 Process Variations 599
15.3 Basic Concepts and Definitions 601
15.4 Design of Experiments and Performance Modeling 608
15.5 Parametric Yield Estimation 615
15.6 Parametric Yield Maximization 621
15.7 Worst-Case Analysis 622
15.8 Performance Variability Minimization 628
References 633
Exercise Problems 633
16 DESIGN FOR TESTABILITY
Introduction
Fault Types and Models
Controllability and Observability
Ad Hoc Testable Design Techniques
Scan-Based Techniques
Built-In Self Test (BIST) Techniques
Current Monitoring IDDQ Test
References
Exercise Problems



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