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VLSI ENGINEERING Complete Lecture notes and PDF
Pankaj Yadav

VLSI ENGINEERING Complete Lecture notes and PDF

Pankaj Yadav | 16-Jan-2016 |
Issues and Challenges in VLSI Design , VLSI Design Methodology , VLSI Design Flow , VLSI Design Hierarchy , CMOS Inverter , Combinational Logic Circuits , Design Capture Tools , Hardware Description Language ,

Hi friends, here Pankaj Yadav uploaded notes for VLSI with title VLSI ENGINEERING Complete Lecture notes and PDF. You can download this lecture notes, ebook by clicking on the below file name or icon.

Module-I (10 Hours)
Issues and Challenges in VLSI Design, VLSI Design Methodology, VLSI Design
Flow, VLSI Design Hierarchy, VLSI Design Styles, CAD Technology. VLSI
Fabrication Technology: Basic Steps of Fabrication, CMOS p-Well and n-Well
Processes, Layout Design, Design Rules, Stick Diagram, Bi-CMOS Fabrication
Process.
Module-II (10 Hours)
CMOS Inverter: MOS Device Model with Sub-micron Effects, VTC Parameters
(DC Characteristics), CMOS Propagation Delay, Parasitic Capacitance Estimation,
Layout of an Inverter, Switching, Short-Circuit and Leakage Components of
Energy and Power; Interconnects: Resistance, Capacitance Estimation, delays,
Buffer Chains, Low Swing Drivers, Power Dissipation, and Performance
Optimization of Digital Circuits by Logical Effort and Transistor Sizing.
Module-III (10 Hours)
Combinational Logic Circuits: Static CMOS Logic Circuits: Complementary
CMOS, Ratioed Logic, Pass Transistor Logic, Transmission Gate Logic, DCVS
Logic, Dynamic CMOS Logic Circuits; Sequential Logic Circuits: Static Latches
and Registers, Dynamic Latches and Registers, Pulse Based Registers; Sense
Amplifier Based Registers, Semiconductor Memories: Non-Volatile and Volatile
Memory Devices, Flash Memories, SRAM, DRAM.
Module-IV (10 Hours)
Design Capture Tools, Hardware Description Language: VHDL, Testing and
Verification: Defects, Fault Models, Design Strategies for Testing, Chip Level and
System Level Test Techniques, Packaging Technology.

 

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